Chip Packaging Solution

Chip Packaging Solution

Wavenics Packaging Technology

Following technologies are patents applied or pending.
SiP(System in Package) Platform technology using selective oxide aluminum board
Technology
Overview
- forms oxide selectively on aluminum board using anodizing type
- Bonding Die (Active element) directly on aluminum board
-> Dissipate heats generated from Die through AI board
- Form wiring and Embedded Passives (R, L, C and Transmission Line) on the oxide formed
Technology No. Description Image implemented with Al board technology
Wa-1 6" Aluminum wafer
- Selective anodizing process
- Form Die Placing Area
- Low-priced Chemical Process
6"Al wafer Form Die Placing Area
Wa-2 Embedded Passives
- Use Thin Film Process
- R, L, C on Al wafer
- Implement High Q inductor
Inductor 2.45GHz BPF
Wa-3 Signal Line
- Form Transmission Line
- Low Insertion Loss
DRAM Package X-Band Tx board
Wa-4 High Density Interconnection
- Form Die Area in accurate size
- Apply film after die mounting
- Form connection with Via-Plating
Connect Via Plating Internal section of Chip mounted
Wa-5 Via formation
- Low-priced chemical process
- Cu-Plating
- Comparison of TSV process of Si, cost < 1/30
Via formation(chemical proceed) Copper Plating
Advantages - Excellent heat dissipation effect (directly attach die on the metal)
(Heat conductivity[W/m·K] : Al2O3 20, Al 230)
- Low cost : manufacturing of board, formation of oxide (chemical process)
- Compact & Slim Size : HEI, Via
-High Isolation : metal board
(1chip of Baseband + RF Module)
- Low cost Via process (chemical process)
- Low Parasitic Inductance
Areas of Application - Baseband (CPU, GPU and MPU) packaging (low footprint and excellent heat dissipation effects)
- RF Module (FEM /FA for WLAN, WIMAX...)
- Base band (CPU) + RF Module (High Isolation) ex) Intel Centrino : single chip possible
- LED Package
Conventional chip packaging method
In the conventional packaging method illustrated in Figure 5.1, the encapsulated molding compound (EMC) surrounding the chip, owing to its low heat conductivity, serves as a major obstacle in the thermal insulation design against heat generated from the chip.
Wavenics, Inc.'s chip packaging method
Figure 5.2 demonstrates our packaging method. Remarkable thermal insulation efficiency is guaranteed by attaching an insulation plate (made of metal) and the chip directly to a groove that is created-based on the PEP method-by vertically etching oxidized layers.
Chip Packaging Solution
 
 
Integrated Passive Devices, RF Module, Aluminum Wafer, High Power Amplifier | Wavenics   Wavenics, Inc. / CEO Daewon Kim
315, Gwangdeok 1-ro, Sangnok-gu, Ansan-si, Gyeonggi-do, Republic of Korea
TEL : +82-42-350-8524 / FAX : +82-42-350-8021
Copyright @ 2007 Wavenics, Inc. All right reserved.